By Naresh Maheshwari
Contemporary years have obvious speedy strides within the point of sophistication of VLSI circuits. at the functionality entrance, there's a very important want for options to layout quickly, low-power chips with minimal quarter for more and more complicated structures, whereas at the monetary part there's the enormously elevated strain of time-to-market. those pressures have made using CAD instruments vital in designing advanced structures.
Timing research and Optimization of Sequential Circuits describes CAD algorithms for reading and optimizing the timing habit of sequential circuits with particular connection with functionality parameters equivalent to energy and sector. A unified method of functionality research and optimization of sequential circuits is gifted. The state-of-the-art in timing research and optimization innovations is defined for circuits utilizing edge-triggered or level-sensitive reminiscence parts. particular emphasis is put on tools which are real sequential timing optimizations options: retiming and clock skew optimization.
Timing research and Optimization of Sequential Circuits covers the subsequent subject matters:
- Algorithms for sequential timing research
- Fast algorithms for clock skew optimization and their purposes
- Efficient concepts for retiming huge sequential circuits
- Coupling sequential and combinational optimizations.
Timing research and Optimization of Sequential Circuits is written for graduate scholars, researchers and pros within the quarter of CAD for VLSI and VLSI circuit layout.
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